High-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical devices, such as input/output (I/O) circuits, CPU power supplies, power management systems, AC/DC converters, etc. There are a variety of forms of HVMOS devices. A symmetric HVMOS device may have a symmetric structure on the source side and drain side. High voltages can be applied on both drain and source sides. An asymmetric HVMOS device may have asymmetric structures on the source side and drain side. For example, only one of the source side and drain side, typically the drain side, is designed for sustaining high voltages.
FIG. 1 illustrates a conventional asymmetric HVPMOS device 2, which includes gate oxide 10, gate electrode 12 on gate oxide 10, drain region 4 in a high-voltage p-well (HVPW) region, and source region 6 in a high-voltage n-well (HVNW) region. Shallow trench isolation (STI) region 8 spaces drain region 4 apart from gate electrode 12, so that a high drain-to-gate voltage can be applied. The HVNW region and HVPW region are formed on an n-type buried layer (NBL).
The conventional HVPMOS device 2 suffers from drawbacks. FIG. 2 illustrates an I-V curve obtained from HVPMOS device 2, wherein the X-axis represents reversed drain-to-source voltages (−Vds), and the Y-axis represents leakage currents (−Ids). It is noted that when operated in a high (reversed) drain-source voltage regions. For example, when high reversed drain-to-source voltages Vds (about −60 volts or greater) are applied, soft breakdown (refer to region 16), which is an undesirable behavior, occurs. Further, the leakage current of HVPMOS device 2 needs to be further reduced. Therefore, a solution for the above-discussed problems is needed.